The development of integrated circuits having densely packed transistors is desirable. One technology that has been developed that allows transistors to be packed tightly together in an integrated circuit (IC) is deep submicron technology. However, the performance of different ICs produced using a same manufacturing process, even on a same wafer, differs.
In some scenarios, the thresholds of MOS transistors on a same IC may be higher, which results in a decrease of a maximum stable operating frequency for that IC and a lower leakage current. In other scenarios, the thresholds of the MOS transistors on a same IC may be lower, which results in an increase of the maximum stable operating frequency for that chip at the expense of a higher leakage current.
By fixed biasing the bodies of the MOS transistors, the thresholds thereof can be set, thereby potentially allowing for adjusting of the balance between operating frequency of the IC and the size of the leakage currents. While this is a useful technique, in some scenarios, further control of the thresholds of the MOS transistors may be desirable. Thus, further development in techniques for biasing the bodies of MOS transistors is needed.